Qualcomm Mask Layout Designer, Senior in Taiwan

Job Description:

Job Id


Job Title

Mask Layout Designer, Senior

Post Date




Qualcomm Technologies, Inc.

CDMA Technology at http://www.qualcomm.com/about/businesses/qct

Job Area

Engineering - Hardware



Job Overview

Design, implement, verify and tapeout process test structures and circuits in advanced sub-10nm nodes to enable process technology team early electrical target definition, device characterization and optimization, and early yield learning.

Minimum Qualifications

5+ years minimum layout design experience in sub-20nm CMOS commercial technologies.

Must have tool experience using

1) Cadence design suite of tools 5.1.4, 6.1., ic12 (layout+schematic)

2) Calibre verification suite (DRC, LVS, ERC, LPE, Softcheck)

3) Design Management tools using Synchronicity's DesignSync

4) UNIX and script automation

Must have relevant test structure design, implementation, verification, assembly and tapeout experience on product testlines. Test structures include, but not limited to, resistors, capacitors, MOSFETs, ring oscillators, matched circuits.

Able to capture, design, develop and implement process technology test structures and circuits that allow easy re-use, with consistency across various layout styles that allow flexible updates with minimal effort.

Ensure layout compliance to Design-Of-Experiment (DOE) documentation and intent. Work with process team device and module owners to translate DOE documentation to functional error-free layouts with minimal supervision.

Knowledeable in layout dependent and parasitic effects. Multi-patterning, finfet techology familarity required.

Independently perform dataprep operations like dummy fill, multi-pattern coloring.

Indepenently debug Calibre verification results with corrections either to layout or schematic in a timely fashion.

Must be physically present and available on-site in Hsin-chu campus 5 days a week, 8 hours a day.

Preferred Qualifications

Experience with foundry technology, Qualcomm intenral tools and Microsoft Excel usage a plus.

Good knowledge of analog sensitive/critical circuits (matching, symmetry, parasitic IR drop identification).

Experience with foundry Cadence techfile, map file setup, ability to use foundry supplied verification decks using Calibre Interactive highly desirable.

Able to write concise daily progress reports on goals.

Education Requirements

Bachelor's, Electrical Engieering or equivalent experience.

EEO Employer: Qualcomm is an equal opportunity employer; all qualified applicants will receive consideration for employment without regard to race, color, religion, sex, sexual orientation, gender identity, national origin, disability, Veteran status, or any other protected classification.