Qualcomm Physical Design Engineer, Staff in Toronto, Ontario
Qualcomm Canada ULC
Engineering Group, Engineering Group > ASICS Engineering
You will be part of a team responsible for the complete Physical Design Flow and deliveries of complex, high-speed, low power designs. Tasks also involve the development and enablement of low power implementation methods, customized P&R to achieve area reduction and performance goals. Additional responsibilities in this role involves good understanding of functional, test (DFT) mode constraints for place and route, floorplanning, power planning, IR drop analysis, placement, multi-mode & multi-corner (MMMC) clock tree synthesis, routing, timing optimization and closure, RC extraction, signal integrity, cross talk noise and delay analysis, debugging timing violations for multi-mode and multi-corner designs, implementing timing fixes, rolling in functional ECOs, debugging and fixing violations and formal verification.
The individual also should have deep knowledge on scripting and software languages including PERL/TCL, Linux/Unix shell and C. This individual will design, verify and delivers complex Physical Design solutions from netlist and timing constraints to the final product.
QCTs DSP Team is actively seeking candidates for several physical design engineering positions in our DSP PD team. As a physical design engineer you will innovate, develop, and implement cores using state-of-the-art tools and technologies.
7+ years industry experience/coursework in the following areas:
Place & Route tool experience on Cadence Innovus and/or Synopsys ICC2, Fusion Compiler
Timing closure experience in Synopsys PrimeTime
Formal verification experience
Physical verification experience
Continuous communication which includes the comprehension of information with colleagues, customers, and vendors both in person and remotely.
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