Qualcomm Audio ASIC Design Engineer, Staff in Toronto, Ontario
Qualcomm Canada ULC
Engineering Group, Engineering Group > ASICS Engineering
You are an ASIC Design Engineer interested in developing world-class audio solutions. The successful candidate must possess internal drive and a keen desire to learn on the job. You will work within a multi-disciplinary, multi-site team of architects, designers and verification engineers and will be responsible for the IP design development and integration within the audio sub-system. The candidate will have strong technical and teamwork skills and will be responsible for overall development and/or integration of various design blocks. You have a disciplined approach to ASIC design and an ability to guide and coach other engineers.
Work independently with little supervision
Develop module specifications and follow through with design and programming specifications
Model and analyze performance, area, power, and system cost tradeoffs for different micro-architectures
Implement modules and sub-systems in Verilog RTL
Develop and update technical documentation on an ongoing basis
Work closely with the design verification team to define verification methodology, review test plans and develop reference and bus-functional models
Implement and debug tests at the module, sub-system and SoC levels throughout the ASIC development cycle (pre- and post-silicon)
Develop and debug synthesis and timing constraints, review clocks, and layout to achieve netlist synthesis and static timing closure
Make significant contributions to silicon debug and analysis
Ability to work legally in Canada
Bachelor's degree in Science, Engineering, or related field.
4 years of ASIC design and/or implementation related experience
Proficiency with Verilog/VHDL RTL design languages
Strong communication (written and verbal) and collaboration skills
Strong understanding of ASIC/VLSI concepts
Detail oriented with strong analytical and debugging skills
6 years of ASIC design related experience
Working knowledge of UPF specification
Experience with power analysis
Experience with High-speed/Low power ASIC design within a Unix environment
Experience with clock domain crossing techniques
Experience with the following design tools:
o ASIC design and simulation tool sets (Synopsys/Cadence Mentor - DC, PTPX, Power Compiler, Primetime, Modeltech, VCS, power theatre, etc.)
o Design rule check (Spyglass, etc.)
o Formal verification (Formality, LEC, etc.)
o Power analysis and simulation
o Scripting languages (PERL, Python, TCL, C, etc.)
Knowledge of bus interface protocols (APB, AHB, AXI)
Experience leading small technical teams
Experience with UVM
• Bachelor's degree in Science, Engineering, or related field and 5+ years of ASIC design, verification, or related work experience.
Master's degree in Science, Engineering, or related field and 4+ years of ASIC design, verification, or related work experience.
PhD in Science, Engineering, or related field and 3+ years of ASIC design, verification, or related work experience.
Applicants : If you need an accommodation, during the application/hiring process, you may request an accommodation by sending email to accommodationsupport
To all Staffing and Recruiting Agencies : Our Careers Site is only for individuals seeking a job at Qualcomm. Staffing and recruiting agencies and individuals being represented by an agency are not authorized to use this site or to submit profiles, applications or resumes, and any such submissions will be considered unsolicited. Qualcomm does not accept unsolicited resumes or applications from agencies. Please do not forward resumes to our jobs alias, Qualcomm employees or any other company location. Qualcomm is not responsible for any fees related to unsolicited resumes/applications.
If you would like more information about this role, please contact Qualcomm Careers (http://www.qualcomm.com/contact/corporate) .
EEO Employer: Qualcomm is an equal opportunity employer; all qualified applicants will receive consideration for employment without regard to race, color, religion, sex, sexual orientation, gender identity, national origin, disability, Veteran status, or any other protected classification.
Equal Employment Opportunity: https://www.eeoc.gov/sites/default/files/migrated_files/employers/poster_screen_reader_optimized.pdf
"EEO is the Law" Poster Supplement : https://www.dol.gov/sites/dolgov/files/ofccp/regs/compliance/posters/pdf/OFCCP_EEO_Supplement_Final_JRF_QA_508c.pdf
Pay Transparency NonDiscrimination Provision: https://www.dol.gov/sites/dolgov/files/ofccp/pdf/pay-transp_%20English_formattedESQA508c.pdf
Employee Polygraph Protection Act: https://www.dol.gov/sites/dolgov/files/WHD/legacy/files/eppac.pdf
Family Medical Leave Act: https://www.dol.gov/sites/dolgov/files/WHD/legacy/files/fmlaen.pdf
Rights of Pregnant Employees: https://www.dfeh.ca.gov/wp-content/uploads/sites/32/2020/12/Your-Rights-and-Obligations-as-a-Pregnant-Employee_ENG.pdf
Discrimination and Harassment: https://www.dfeh.ca.gov/wp-content/uploads/sites/32/2020/10/Workplace-Discrimination-Poster_ENG.pdf
California Family Rights Act: https://www.dfeh.ca.gov/wp-content/uploads/sites/32/2020/12/CFRA-and-Pregnancy-Leave_ENG.pdf