Qualcomm Senior Design verificaton Engineer in Shanghai, China
Senior Design verificaton Engineer
Qualcomm Technologies, Inc.
CDMA Technology at http://www.qualcomm.com/about/businesses/qct
Engineering - Verification
China - Shanghai
Digital Verification of communication chips. The verification work includes: developing testbenches; write plan development; run regression and debugging. The candidates shall have solid background in UVM and system Verilog. Its a big plus is he or she has work experience on digital signal processing/Matlab/C++.
The responsibilities of this role include:
Define testbench infrastructure using System Verilog, UVM and maybe Formal.
Assist in complete verification of high performance, high speed, low power ASIC.
Work closely with system architect and design managers to architect a new design verification environment and produce high quality verification closure.
Guide the development of comprehensive, flexible, and portable block to chip level testbench, detailed test plans and coverage closure.
PRINCIPAL DUTIES AND RESPONSIBILITIES:
Set up DV environment based on UVM.
Writes tests and regressions to identify any bugs in design
Executing verification through direct and random tests. Debugging regression failures and identify the cause.
Creation of needed test libraries, simulation models.
Infrastructure work including developing scripts, methodologies and tools for efficiency and quality improvements
Bachelor's degree in Science, Engineering, or related field.
2+ years ASIC design, verification, or related work experience.
Bachelor's degree in Electrical Engineering, Computer Science, or Computer Engineering.
3+ years ASIC digital verification experience.
3+ years experiences with UVM.
EEO Employer: Qualcomm is an equal opportunity employer; all qualified applicants will receive consideration for employment without regard to race, color, religion, sex, sexual orientation, gender identity, national origin, disability, Veteran status, or any other protected classification.