Qualcomm Physical Design Engineer in Shanghai, China
Physical Design Engineer
Qualcomm Atheros Inc
Qualcomm Atheros at http://www.qualcomm.com/about/businesses/qca
Engineering - Hardware
China - Shanghai
Responsible for STA and timing closure
Responsible to co-work with physical design team for timing closure, signal integrity, power integrity
Responsible to setup STA flow and timing closure flow automation.
Responsible to develop timing constraint and low power design constraint
Responsible to optimize digital frontend flow qualification
Bachelor's degree in Science, Engineering, or related field.
2+ years ASIC design, verification, or related work experience.
Good knowledge of digital logic design, synthesis, STA, formal verification, etc.
Good experience with Design compiler, Prime time and timing ECO tools
Solid skill sets of STA and timing closure relative EDA tools.
Knowledge of DFT or physical design is a plus
Familiar with common UNIX utility such as Shell, Perl, TCL
Experience in SoC chip integration and chip design quality improvement is a plus.
Experience in tapeout with multi-million gates count SOC design, 28/16/14nm design experience is a plus.
Good English communication skills
Self-motivated and good team player
EEO Employer: Qualcomm is an equal opportunity employer; all qualified applicants will receive consideration for employment without regard to race, color, religion, sex, sexual orientation, gender identity, national origin, disability, Veteran status, or any other protected classification.