Job Information
Qualcomm Staff SOC Physical Design Engineer in Santa Clara, California
Company:
Qualcomm Atheros, Inc.
Job Area:
Engineering Group, Engineering Group > ASICS Engineering
General Summary:
A SOC Physical Design Engineer plays a crucial role in the development and implementation of products at Qualcomm. This role requires strong knowledge of physical design tools (like Cadence or Synopsys), semiconductor processes, and an understanding of timing closure, clock tree synthesis, power optimization, and physical verification methodologies. Additionally, communication skills and the ability to work in a multi-geo team are essential for success in this role.
Minimum Qualifications:
• Bachelor's degree in Science, Engineering, or related field and 4+ years of ASIC design, verification, validation, integration, or related work experience.
OR
Master's degree in Science, Engineering, or related field and 3+ years of ASIC design, verification, validation, integration, or related work experience.
OR
PhD in Science, Engineering, or related field and 2+ years of ASIC design, verification, validation, integration, or related work experience.
Preferred Qualifications:
• Master's degree in Electrical/Electronic Engineering, Computer Engineering, or Computer Science.
• 6+ years of ASIC design, verification, validation, integration, or related work experience.
• 2+ years of experience with architecture and design tools.
• 2+ years of experience with scripting tools and programming languages.
• 2+ years of experience with design verification methods.
• 1+ year of work experience in a role requiring interaction with senior leadership (e.g., Director level and above).
Principal Duties & Responsibilities:
Physical Design: Handling the physical design activities and closure of complex sub-system blocks, ensuring adherence to design specifications and requirements.
Floorplanning: Creating block floorplans, considering various factors like power, performance, area, and routing congestion to optimize the layout.
Timing Closure: Ensuring that the block meets timing requirements of the chip’s subsystem , by optimizing clock tree synthesis, placement, routing and timing ECOs.
Place and Route: Executing placement and routing of logic gates and interconnects, optimizing for performance (timing), power, and area.
Power Optimization: Implementing power-saving techniques and strategies to meet low-power design goals.
Physical Verification: Conducting design rule checks (DRC), layout versus schematic (LVS) checks, ERC and other miscellaneous checks to ensure the physical design meets manufacturing requirements.
Power Integrity: Ensuring that the block/chip meets the strict constraints of IR drop, Electromigration, ESD path resistance and inrush current checks
Formal Verification: Ensuring that the design’s post-layout functionality meets the intention of the netlist delivered by front-end designers
Collaboration: Working closely with cross-geo front-end design teams, CAD engineers, other physical design and cross-functional teams to achieve project goals and resolve design challenges.
Methodology Development: Participating in the development and improvement of physical design methodologies, flows and tools to enhance efficiency and quality of chip designs.
Level of Responsibility:
• Works independently with minimal supervision.
• Provides supervision/guidance to other team members.
• Decision-making is significant in nature and affects work beyond immediate work group.
• Requires verbal and written communication skills to convey complex information. May require negotiation, influence, tact, etc.
• Has a moderate amount of influence over key organizational decisions (e.g., is consulted by senior leadership to make key decisions).
• Tasks do not have defined steps; planning, problem-solving, and prioritization must occur to complete the tasks effectively.
Although this role has some expected minor physical activity, this should not deter otherwise qualified applicants from applying. If you are an individual with a physical or mental disability and need an accommodation during the application/hiring process, please call Qualcomm’s toll-free number found here (https://qualcomm.service-now.com/hrpublic?id=hr_public_article_view&sysparm_article=KB0039028) for assistance. Qualcomm will provide reasonable accommodations, upon request, to support individuals with disabilities as part of our ongoing efforts to create an accessible workplace.
Qualcomm is an equal opportunity employer and supports workforce diversity.
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EEO Employer: Qualcomm is an equal opportunity employer; all qualified applicants will receive consideration for employment without regard to race, color, religion, sex, sexual orientation, gender identity, national origin, disability, Veteran status, or any other protected classification.
Qualcomm expects its employees to abide by all applicable policies and procedures, including but not limited to security and other requirements regarding protection of Company confidential information and other confidential and/or proprietary information, to the extent those requirements are permissible under applicable law.
Pay range:
$143,000.00 - $215,000.00
The above pay scale reflects the broad, minimum to maximum, pay scale for this job code for the location for which it has been posted. Even more importantly, please note that salary is only one component of total compensation at Qualcomm. We also offer a competitive annual discretionary bonus program and opportunity for annual RSU grants (employees on sales-incentive plans are not eligible for our annual bonus). In addition, our highly competitive benefits package is designed to support your success at work, at home, and at play. Your recruiter will be happy to discuss all that Qualcomm has to offer!
If you would like more information about this role, please contact Qualcomm Careers (http://www.qualcomm.com/contact/corporate) .
EEO Employer: Qualcomm is an equal opportunity employer; all qualified applicants will receive consideration for employment without regard to race, color, religion, sex, sexual orientation, gender identity, national origin, disability, Veteran status, or any other protected classification