Qualcomm Staff ASIC Design Engineer – Next Generation, High Speed Memory Subsystem Design in San Diego, California

Job Description:

Job Id


Job Title

Staff ASIC Design Engineer – Next Generation, High Speed Memory Subsystem Design

Post Date




Qualcomm Technologies, Inc.

CDMA Technology at http://www.qualcomm.com/about/businesses/qct

Job Area

Engineering - Hardware


California - San Diego

Job Overview

QCT Memory Subsystem Design Team is looking for talented ASIC Design Engineers for the next generation, high-speed (1 GHz+) DDR Memory Subsystem development for Qualcomms flagship Snapdragon devices. The Memory Subsystem integrates state-of-the art memory/cache controllers, PHYs, front-end and back-end infrastructure components. The front-end of the memory subsystem interfaces to rest of the system such as CPU, DSP, Multimedia processors.

The candidate will work on architecture, design, and deployment of the memory subsystem into QCT products. You will contribute to the development of design specification, micro-architecture aspects of the logic design. You will implement and deliver RTL, interface with verifications engineers to deliver high quality designs. You will be responsible for debugging your design, and provide debug support as part of memory subsystem integration at the SoC level. Synthesis, Timing Closure, Power Analysis, Gate Level Simulations, Physical Design Support, are expected to be key tasks, besides RTL coding. You are expected to contribute to overall improvement in ASIC design methodology to drive productivity and quality of results.

All Qualcomm employees are expected to actively support diversity on their teams, and in the Company.

Minimum Qualifications

  • Bachelor's degree in Science, Engineering, or related field.

  • 5+ years ASIC design, verification, or related work experience.

Preferred Qualifications

Bachelors degree in Electrical or Computer Engineering and at least 5-7 years of hands-on experience in high speed digital design. Experience with the following:

  • DDR controller architectures especially the front end interfacing to the CPU, DSP, and multimedia processors

  • On-chip tightly coupled SRAM & L3 cache controller architecture/design

  • Experience with x86 or ARM CPU/bus architectures

  • Experience with ASIC front-end design/synthesis flows

  • Exposure to RTL verification flows is a plus

Education Requirements

Required: Bachelor's, Computer Engineering and/or Electrical Engineering

Preferred: Master's, Computer Engineering and/or Electrical Engineering

EEO Employer: Qualcomm is an equal opportunity employer; all qualified applicants will receive consideration for employment without regard to race, color, religion, sex, sexual orientation, gender identity, national origin, disability, Veteran status, or any other protected classification.