Qualcomm Sr. Eng. - ASIC Digital Design in San Diego, California

Job Description:

Job Id


Job Title

Sr. Eng. - ASIC Digital Design

Post Date




Qualcomm Technologies, Inc.

CDMA Technology at http://www.qualcomm.com/about/businesses/qct

Job Area

Engineering - Hardware


California - San Diego

Job Overview

Responsibilities include:

  • Digital design and analog/mixed signal design support for PLL, DAC, ADC and other mixed-signal designs.

  • Digital design aspects include full behavioral level description with high level synthesis languages and gate level synthesis, logic level synthesis, timing closure, power and signal integrity analysis and testability.

  • Analog/mixed-signal support includes behavioral modeling of RF and analog blocks using Verilog in the cadence AMS environment and analog/digital integration and verification methodologies using Cadence AMS.

  • Work in a dynamic team environment with aggressive schedule, chip power consumption and area targets.

All Qualcomm employees are expected to actively support diversity on their teams, and in the Company.

Minimum Qualifications

  • Bachelor's degree in Science, Engineering, or related field.

  • 2+ years ASIC design, verification, or related work experience

Preferred Qualifications

5 years of relevant experience with the following:

  • Digital ASIC design including architecture

  • RTL design for control and datapath, linting, synthesis, STA, and DFT

  • Experience with leading-edge ASIC development tools from Synopsys, Mentor, or Cadence

Education Requirements

Required: Bachelor's, Computer Engineering and/or Electrical Engineering

Preferred: Master's, Computer Engineering and/or Electrical Engineering

EEO Employer: Qualcomm is an equal opportunity employer; all qualified applicants will receive consideration for employment without regard to race, color, religion, sex, sexual orientation, gender identity, national origin, disability, Veteran status, or any other protected classification.