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Qualcomm SERDES/DDR/D2D Interface Systems Engineer (Senior/Staff Engineer/Sr. Staff Engineer) in San Diego, California


Qualcomm Technologies, Inc.

Job Area:

Engineering Group, Engineering Group > ASICS Engineering

General Summary

Mixed signal systems group resides in Mobile Business Unit of Qualcomm Technology Inc., a leader in wireless communication technology. Engineers in the Mixed signal Systems group work on mixed signal IP architecture, interface standards, system-technology co-optimization, power and signal integrity, hardware/software co-design and post-Silicon bring-up to help create leading edge mobile and compute products.

Group has multiple open positions and is looking for engineers at junior to senior levels with knowledge and experience in SERDES, DDR or 2D/3D Die-to die(D2D) interface IP and systems design. A successful candidate will be involved in SERDES/DDR/D2D interface roadmap and spec definition, package/foundry technology co-optimization, signal/power integrity analysis and system KPI evaluations. The person will also work very closely with the cross-functional platform architecture, process technology, package engineering and IP and SoC development teams to successfully develop, test and deploy the design to end-product. Working effectively across organizational boundaries is essential as is effective documentation and presentation of results.


  • SERDES/DDR/D2D interface roadmap and system design exploration

  • System models for early evaluations and spec definition

  • Translate product requirements to SERDES/DDR/D2D IP system design spec.

  • System-technology co-optimization - SIPI, PDN, floorplan, PKG/PCB/Foundry technology, and IP PPA trade-off analysis to optimize system metrics such as cost, power, performance, and quality.

  • Interface with cross-functional teams through various phases of the project to successfully integrate and validate the design.

  • Support silicon bring up and debug effort for SERDES/DDR/D2D interfaces.

  • Support post-Si correlation efforts and feedback to early design/proto-typing flows.

  • Develop best known methods and establish guidelines for design teams to follow.

  • Create clear and complete documentation of guidelines and results.

Minimum Qualifications

Education: Bachelor's degree in Science, Engineering, or related field.

Work experience: 2+ years ASIC and Phy designs, post silicon bring-up & debug, or related work experience.

Preferred Qualifications

Education: MS or PhD in Electrical Engineering, or related discipline

Work experience:

Knowledge of SERDES/DDR/D2D standards is preferred.

Experience in high-speed Serdes or DDR Phy design is preferred.

Familiarity with SERDES/DDR/D2D protocol and post-Si debug is a plus.


o Ansys, Cadence, Keysight and Matlab Tools, Hspice, Verilog


  • Frequently transports between offices, buildings, and campuses up to ½ mile.

  • Frequently transports and installs equipment up to 5 lbs.

  • Performs required tasks at various heights (e.g., standing or sitting).

  • Monitors and utilizes computers and test equipment for more than 6 hours a day.

  • Continuous communication which includes the comprehension of information with colleagues, customers, and vendors both in person and remotely.

Minimum Qualifications


Bachelors - Engineering, Bachelors - Science

Work Experiences:

2+ years ASIC design, verification, or related work experience.



Preferred Qualifications


Work Experiences:



ASIC Verification, Matlab C, Multicore System-On-Chip (SoC), Perl Programming, Simulation Software

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EEO Employer: Qualcomm is an equal opportunity employer; all qualified applicants will receive consideration for employment without regard to race, color, religion, sex, sexual orientation, gender identity, national origin, disability, Veteran status, or any other protected classification.

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