Qualcomm ASIC Design Verification Engineer - Video Compute DSP / AI Processors in Markham, Ontario
Qualcomm Canada ULC
Engineering Group, Engineering Group > ASICS Engineering
QUALCOMM is the world's leading developer of next-generation wireless and multimedia technology. Be part of the group that is working on technology that will bring cognition to all connected devices: meaning devices that don’t just think, but instinctively react to their surroundings. Join the Video Analytics and Processing team responsible for ASIC IP design, verification, and integration of leading-edge image post processing, computational imaging, machine learning, and IoT technologies.
We are searching an ASIC verification engineer interested in developing world-class multimedia and compute solutions to build next generation mobile System-on-Chips (SoCs).
Verification and modelling of multimedia and compute ASIC modules and sub-systems:
Verify the features and performance of IP-level RTL using coverage-driven, constrained-random methodologies in System Verilog (i.e. UVM/OVM)
Create comprehensive verification plans to describe the functional/feature test points of the DUT, and present the plan to the IP team
Develop reusable testbench components such as scoreboards, reference models, checkers, drivers, monitors, and VIPs using SystemVerilog/UVM and C/C++ Create functional coverage models to track the IP verification quality relative to the DV plan
Develop SVA assertions for functional and formal verification
Implement verification methodology and automation using scripts (e.g. Python, Perl)
Create performance verification monitors, models, and test scenarios
Develop and support a regression and coverage flow to ensure high DV quality
Bachelors or master’s degree in Engineering or Engineering Science
3+ years’ experience design and/or verification of ASIC IP
Proven experience verifying Verilog and/or System Verilog RTL designs
Working experience using testbench components such as Interface VIPs, reference models, scoreboards, transactors
Experience with several of the following tools/techniques
Functional model development (UVM, SystemC, SVAs, and/or C++)
Simulation and code coverage tools (VCS, Verdi, Modeltech/Questa, or Xcelium)
Design rule and Multi-frequency and CDC verification (SVA assertions)
Bus implementation/verification techniques
Verification automation using Python, PERL, or other scripting languages
Practiced verification of one or more of the following
Data and/or image processing pipelines
Clock domain crossing and Reset architecture
Bus interface protocols (APB, AHB, AXI) and RTL
FIFOs and memory controllers
Detail oriented with strong analytical and debugging skills
Strong communication (written and verbal), collaboration, and specification skills
Videos : ASIC - https://lnkd.in/d-We6w3Y, Qualcomm: https://www.youtube.com/watch?v=Sh5HO1L4MUk ; https://www.youtube.com/watch?v=Ros6VQqcuVc
• Bachelor's degree in Science, Engineering, or related field and 5+ years of ASIC design, verification, or related work experience.
Master's degree in Science, Engineering, or related field and 4+ years of ASIC design, verification, or related work experience.
PhD in Science, Engineering, or related field and 3+ years of ASIC design, verification, or related work experience.
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