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Qualcomm RTL/Digital Design Engineer in Bangalore, India


Qualcomm India Private Limited

Job Area:

Engineering Group, Engineering Group > Hardware Engineering

General Summary:

Skills & Experience

  • MTech/BTech in EE/CS with hardware engineering experience of 6-10 years.

  • Experience in micro-architecture development, RTL design, front-end flows (Lint, CDC, low-power checks, etc.), synthesis/DFT/FV/STA.

  • Experience with DDR PHY design and good understanding of DDR protocols like LPDDR3/4/5, PCDDR3/4/5, etc. is desirable.

  • Experience with post-silicon bring-up and debug is a plus.

  • Able to work with teams across the globe and possess good communication skills.


  • RTL development and its validation for linting, clock-domain crossing and DFT rules.

  • Work with functional verification team on test-plan development and debug.

  • Develop timing constraints, deliver synthesized netlist to physical design team and provide constraints support for PD STA.

  • UPF writing, power aware equivalence checks and low power checks.

  • DFT insertion and ATPG analysis for optimal SAF, TDF coverage.

  • Provide support to SoC integration and chip level pre/post-silicon debug.

Minimum Qualifications:

• Bachelor's degree in Computer Science, Engineering, Information Systems, or related field and 2+ years of Hardware Engineering or related work experience.


Master's degree in Computer Science, Engineering, Information Systems, or related field and 1+ year of Hardware Engineering or related work experience.


PhD in Computer Science, Engineering, Information Systems, or related field.

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