Qualcomm LPASS Design Verification Sr Lead Engineer in Bangalore, India
Qualcomm India Private Limited
Engineering Group, Engineering Group > Hardware Engineering
Qualcomm LPASS HW team in Bangalore is part of a worldwide team responsible for developing and delivering Audio solutions which are setting the benchmark in mobile computing industry. The role of LPASS DV Engineer will involve a deep understanding of the HW architecture while getting an opportunity to work with the latest DV tools and technologies.
Individual responsibility will include
• DV ownership of one or more features in the Low power audio subsystem(LPASS) core
• Developing a robust testbench, optimized for the specific feature/DUT
• Explore innovative DV methodologies (formal, simulation and emulation based) to continuously push the quality and efficiency of test benches and process improvements.
• Ensure a bug free silicon for Tape Out which eventually leads to a superb user experience of Snapdragon based computing devices
• Minimum 3-6 years of VLSI industry experience
• Strong debugging and analytical skills
• Strong knowledge of HDLs like Verilog, System Verilog
• Proficiency in developing SV/UVM based test benches
• Proficient in debugging RTL/TB issues using Verdi or similar tools
• Proficient with scripting languages such as Perl and(or) Python
Preferred Qualifications *
• Knowledge of UPF, low power architecture
Applicants : If you need an accommodation, during the application/hiring process, you may request an accommodation by sending email to accommodationsupport
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EEO Employer: Qualcomm is an equal opportunity employer; all qualified applicants will receive consideration for employment without regard to race, color, religion, sex, sexual orientation, gender identity, national origin, disability, Veteran status, or any other protected classification.
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