Qualcomm Jobs

Job Information

Qualcomm Layout Engineer - PMIC in Bangalore, India


Qualcomm India Private Limited

Job Area:

Engineering Services Group, Engineering Services Group > Layout Engineer

General Summary:

Minimum Qualifications:


Develops block, macro, or chip level layouts and floorplans according to project requirements, specifications, and design schematics. Applies understanding of design manuals, established processes, layout elements, and basic electronic principles to create accurate designs that meet project needs. Conducts analyses, tests, and verifies designs using different tools and techniques to identify and troubleshoot issues, and stays abreast of new verification methods. Works with multiple internal and external stakeholders to align on projects, provide updates, and resolve issues.

The responsibilities of this role include:

• Works under some supervision.

• Provides some supervision/guidance to other members; does not have direct reports.

• Decisions are moderate in nature. Errors are detected and corrected with relatively minor financial impact or effect on projects, operations, or customer relationships. May require involvement beyond immediate work group to correct.

• Requires verbal and written communication skills to convey information that may be somewhat complex to others who may have limited knowledge of the subject in question. Role may require basic negotiation and influence, cooperation, tact, and diplomacy, etc.

• Has a moderate amount of influence over key organizational decisions (e.g., is consulted by senior leadership to make key decisions).

• Most tasks require multiple steps which can be performed in various orders; some planning and prioritization must occur to complete the tasks effectively; mistakes may result in some rework.

• Creativity is needed to draft original documents, imagery, or work products within established guidelines.

• Deductive and inductive problem solving is required; multiple approaches may be taken/necessary to solve the problem; often information is missing or incomplete; intermediate data analysis/interpretation skills may be required.

• Incumbent's input may be solicited during strategic planning period.

The responsibilities of this role do not include:

• Does not have financial accountability.


• Reads and develops complex project requirements and specifications; interprets schematics to understand macro-level design needs and helps team members do the same.

• Defines and builds macro level layouts and floorplans based on advanced understanding of layout techniques, design elements, and electronic principles (e.g., currents, resistance, parasitic).

• Adheres to and helps team understand established guidelines, processes, design rule manuals, and checklists to ensure designs are high-quality, accurate, and meet standards; identifies ways to improve guidelines and manuals.

• Leads the testing and validation of macro level designs against specifications using layout and verification tools (e.g., Cadence, LVS, rmap) to identify and resolve errors.

• Coordinates gathering and interpreting information and conducts analyses and sign-off to identify where an issue has occurred; troubleshoots and debugs complex technical issues.

• Proposes and works with team to implement ideas for improving or automating processes and practices to better accomplish work.

• Stays abreast of industry trends and developments related to mask layout tools and techniques; shares best practices with team members and helps others understand concepts.

• Leads team to adapt to significant changes and setbacks in order to manage pressure and meet deadlines.

• Manages team project priorities, deadlines, and deliverables for small to mid-sized projects.

• Partners with engineers, cross-functional teams, and some external stakeholders to align on needs, facilitate information sharing, and troubleshoot complex issues.

Candidate needs to have 7+ years of hands on experience on various Power Management (PMIC) Module layouts, physical verification using Calibre Verification suite.

Skill sets needs to include but not limited to the following:

  • Extensive floorplanning and signal planning skills in Cadence Virtuoso IC201.

  • Layout Design for various analog circuits like: Linear and Switching Regulators, ADCs, DACs, CHARGERS, Envelope Trackers, APTs, High Current POWERFETS, OTAs, Error Amplifiers, etc.

  • Strong understanding of submicron, deep-submicron, Triple Well, High Voltage CMOS processes. SOI process knowledge is an advantage.

  • Very strong Analog Layout fundamentals and basic electrical knowledge for layout development.

  • Strong physical verification debugging capability using Calibre Verification Suite.

  • Create area and parasitic efficient layouts, with strong problem solving skills.

  • Ability to perform in a dynamic, Team Oriented environment.

  • Well-developed organizational skills and the ability to multi-task.

  • Scripting knowledge in SKILL/PERL/SHELL is an advantage.

  • Strong communication skills for efficient delivery. Team player skills to work with geographically spread team members.

  • Create technical documentation and presentations.

Applicants : If you need an accommodation, during the application/hiring process, you may request an accommodation by sending email to accommodationsupport

To all Staffing and Recruiting Agencies : Our Careers Site is only for individuals seeking a job at Qualcomm. Staffing and recruiting agencies and individuals being represented by an agency are not authorized to use this site or to submit profiles, applications or resumes, and any such submissions will be considered unsolicited. Qualcomm does not accept unsolicited resumes or applications from agencies. Please do not forward resumes to our jobs alias, Qualcomm employees or any other company location. Qualcomm is not responsible for any fees related to unsolicited resumes/applications.

If you would like more information about this role, please contact Qualcomm Careers (http://www.qualcomm.com/contact/corporate) .

EEO Employer: Qualcomm is an equal opportunity employer; all qualified applicants will receive consideration for employment without regard to race, color, religion, sex, sexual orientation, gender identity, national origin, disability, Veteran status, or any other protected classification.

Equal Employment Opportunity: https://www.eeoc.gov/sites/default/files/migrated_files/employers/poster_screen_reader_optimized.pdf

"EEO is the Law" Poster Supplement : https://www.dol.gov/sites/dolgov/files/ofccp/regs/compliance/posters/pdf/OFCCP_EEO_Supplement_Final_JRF_QA_508c.pdf

Pay Transparency NonDiscrimination Provision: https://www.dol.gov/sites/dolgov/files/ofccp/pdf/pay-transp_%20English_formattedESQA508c.pdf

Employee Polygraph Protection Act: https://www.dol.gov/sites/dolgov/files/WHD/legacy/files/eppac.pdf

Family Medical Leave Act: https://www.dol.gov/sites/dolgov/files/WHD/legacy/files/fmlaen.pdf

Rights of Pregnant Employees: https://www.dfeh.ca.gov/wp-content/uploads/sites/32/2020/12/Your-Rights-and-Obligations-as-a-Pregnant-Employee_ENG.pdf

Discrimination and Harassment: https://www.dfeh.ca.gov/wp-content/uploads/sites/32/2020/10/Workplace-Discrimination-Poster_ENG.pdf

California Family Rights Act: https://www.dfeh.ca.gov/wp-content/uploads/sites/32/2020/12/CFRA-and-Pregnancy-Leave_ENG.pdf