Qualcomm Frontend /RTL ENGINEER in Bangalore, India

Job Description:

Job Id

E1968426

Job Title

Frontend /RTL ENGINEER

Post Date

12/03/2018

Company


Division

Qualcomm Technologies, Inc.


CDMA Technology at http://www.qualcomm.com/about/businesses/qct

Job Area

Engineering - Hardware

Location

India - Bangalore

Job Overview

This position is open for 6-10 years experience candidate in Qualcomm CSI (Custom/SemiCustom implementation) team

Candidate will be part of CSI team working on RTL- GDS HM implementations using custom flow and methodology for CSI IPs .

Qualcomm is one of the fastest growing semiconductor organization in India making high-end Chips with the most advanced technologies. To support its growing needs, we have strong CSI team for the design, development of various highspeed and low power IPs being used in SoC. Individual has to work on RTL-GDS implementation. This will involve innovating new solutions in close collaboration with the other design teams.

Job Responsibilities:

Job responsibilities include design and development of custom macro using

Synthesis, formal verification , Design verification, for digital IPs

CLP, PAGLS verifications

UPF/CPF methodology.

Candidate should be able to collaborate with different teams.

Minimum Qualifications

  • Bachelor's degree in Engineering, Information Systems, Computer Science, or related field.

  • 6+ years Hardware Engineering experience or related work experience.

Preferred Qualifications

Front-end RTL Design (Verilog RTL design, System Verilog, Synopsys Design Compiler, Cadence RTL Compiler, LEC, PLDRC, Static Timing Analysis and PTPX)

Design verification using ESPCV & LEC, Simulation using Finesim & HSPICE.

Strong knowledge in RTL, verification, synthesis flow

STA for the design to close Set-up, Hold, MPW, Transition, etc

Scripting in Perl/Python/Shell/Tcl for productivity is a plus

IP development (custom macro transistor level design, physical integration, collateral generation, flow development) and PPA quantification.

Work with cross functional teams (Architecture, Test/Verification , Product, CAD, Layout, Physical Design) to gather/define/implement specs

Implement power/clock gating techniques, implement power/clock gating techniques, Implement industry standard as well as custom DFT techniques

Physical Design using industry-standard RTL2GDS flow including Synopsys ICC2, Cadence Encounter.

Scripting in Perl/Python/Shell/Tcl for productivity is a plus

IP development (custom macro transistor level design, physical integration, collateral generation, flow development) and PPA quantification.

Interface with Process Technology Team to understand the complex DRC and DFM requirements of the advanced technology nodes

Work with cross functional teams (Architecture, Test/Verification , Product, CAD, Layout, Physical Design) to gather/define/implement specs

Transistor level implementation of the block using CMOS/Domino/Cell-Based/Data path styles

Implement power/clock gating techniques, Implement power/clock gating techniques, Implement industry standard as well as custom DFT techniques

Implement clock distribution using custom/CTS techniques for low skew/latency/power, Implement block layout using custom/compiler techniques using custom/semi-custom/stdcell libraries

Implement block level floor planning using custom and/or tiling techniques

Education Requirements

  • Bachelor's degree in Engineering, Information Systems, Computer Science, or related field.

EEO Employer: Qualcomm is an equal opportunity employer; all qualified applicants will receive consideration for employment without regard to race, color, religion, sex, sexual orientation, gender identity, national origin, disability, Veteran status, or any other protected classification.