Qualcomm ASIC Design Manager (CPU/Processor Design) in Bangalore, India
ASIC Design Manager (CPU/Processor Design)
Qualcomm Technologies, Inc.
CDMA Technology at http://www.qualcomm.com/about/businesses/qct
Engineering - Hardware
India - Bangalore
This position is for RTL Design Manager role of complex Qualcomm propriety Hexagon DSP IP
DSP design team is responsible for delivering high-performance DSP cores which are at the heart of Qualcomm's multi-tier SoC roadmap targeted for mobile space
The position involves people management as well as technical management of highly accomplished RTL team of 15 people
Candidate must have in-depth understanding of the ASIC design flow from RTL to GDS2 and the challenges posed by advanced technologies
The successful candidate will possess detailed understanding of RTL design, synthesis, static timing analysis, formal verification, PLDRC, clock domain crossing, and low power techniques
Knowledge and experience of microprocessor integration is a definite advantage.
Drive RTL design of DSP IP by working with a global DSP design team involving architecture, implementation, post silicon and back-end teams
Implement and improve RTL and DSP Architecture
Develop RTL for multiple logic blocks of a DSP core
Run various frontend tools to check for linting, clock domain crossing, synthesis, etc.
Work with physical design team on design constrain and timing closure
Work with power team on power optimization
Work with verification team to collaborate on test plan, coverage plan, and coverage closure
Bachelor's degree in Engineering, Information Systems, Computer Science, or related field.
7+ years Hardware Engineering experience or related work experience.
15-20 years experience in processor/ASIC design
Solid background and understanding of Digital Design, RTL development and Processor Architecture
Practical experience in functional and structural RTL design, design partitioning, simulation and regression, collaboration with design verification team.
Must have good familiarity with latest RTL languages and tools, including: simulation systems (e.g. Modelsim, VCS), synthesis tools (e.g. Design Compile), static timing tools (e.g. Prime Time), Linting tools, CDC tools, UPF, code coverage, System Verilog Assertion, etc.
Experience with the following area is highly desirable:
Strong processor architecture knowledge
Low power design
Excellent verbal and written communication skills. Ability to work in a team environment. Good self-direction and time management skills
Experience in AMBA, AHB, AXI, JTAG and debug protocols
Gate-Level Simulation and Debug 0-delay, timing annotated and power aware
Experience is verification of Processor subsystems (ARM/DSP) is preferred
Exposure to silicon bring up, silicon testing , bench and application testing is a definite plus
Required: Bachelor's, Electrical Engineering
Preferred: Master's, Electrical Engineering
EEO Employer: Qualcomm is an equal opportunity employer; all qualified applicants will receive consideration for employment without regard to race, color, religion, sex, sexual orientation, gender identity, national origin, disability, Veteran status, or any other protected classification.